1. Field of the Invention
The present invention generally relates to a source follower with Vgs compensation, and more particularly, to a source follower such that the output voltage precisely follows the input voltage by various arrangements of metal-oxide-semiconductor transistors (to be abbreviated as MOSFET""s hereinafter), switches, and capacitors.
2. Description of the Prior Art
The technique in the field of displays has grown rapidly due to the fast development in opto-electronics. However, for a thin film transistor-liquid crystal display (to be abbreviated as TFT-LCD hereinafter), the implementation of the driving circuit for such a display has been a key technique. To more specific, the circuit design for source follower implementation has a lot to be improved.
Please refer to FIG. 1A, which shows a conventional source follower circuit, wherein a single n-MOSFET is provided with the drain terminal connected to a constant voltage source, the gate terminal receiving an input voltage and the source terminal outputting an output voltage. Since the bias current that flows through such a MOSFET is fixed, in other words, the current I is a constant, the voltage across the gate terminal and the source terminal, Vgs, is kept fixed. Therefore, as the gate terminal is applied with an input voltage Vin, the source voltage Vout is determined from inspection of the circuit to be Vout=Vinxe2x88x92Vgs. Similarly, as shown in FIG. 1B, a single p-MOSFET is provided with the drain terminal connected to a constant voltage source, the gate terminal receiving an input voltage and the source terminal outputting an output voltage. Therefore, as the gate terminal is applied with an input voltage Vin, the source voltage Vout is determined from inspection of the circuit to be Vout=Vinxe2x88x92Vgs.
Nevertheless, such a circuit configuration suffers from the problems in that (1) there exists a difference value of Vgs between Vout and Vin, (2) MOSFET""s at different positions have different threshold voltages, Vt, because there are a lot of buffers used in a large area, leading to a varying Vgs due to the relation Vgs=Vt+xcex94V, wherein xcex94V denotes a voltage variation, resulting in inaccuracy and poor uniformity, and (3) Vout varies with Vin as the change in Vds leads to the change in Vgs. In brief, Vout=Vinxe2x88x92Vgsxe2x88x92xcex94Vgs. Accordingly, Vout varies with xcex94Vgs (dVgs is about 50 mV when Vin is from 0 to 10 V.) In operation, such a circuit configuration can serve as a data driver when speed is concerned, however, it still has a lot to be improved when precision is taken into account.
The prior art technique can be exemplified by, for example, xe2x80x9c16.4 A Low-Power Poly-Si TFT-LCD with Integrated 8-bit Digital Data Driversxe2x80x9d, SID 1998, xe2x80x9cHigh Performance, Low-Power Integrated 8-bit Digital Data Driver for Poly-Si TFT-LCDxe2x80x9d, SID 1999, and xe2x80x9cA Novel Integrated Serial Data Driver Poly-Si TFT-LCD""sxe2x80x9d, ED 1999. All of these articles were completed by the group conducted by Seung-Woo Lee at Taejon University, Korea.
For the key points disclosed in the above three articles, please refer to FIG. 2A and FIG. 2B, wherein FIG. 2A shows the circuit configuration of a digital data driver in the prior art and FIG. 2B shows a switching waveform diagram for the switches according to FIG. 2A. If the output voltage is in the ranges from 0 to 5 V and from 5 to 10 V, there are provided an n-MOSFET in charge of the range from 5 to 10 V and a p-MOSFET in charge of the range from 0 to 5 V. For each input data, only one of n-MOSFET and p-MOSFET operates in the saturation region and the other is cut off. Furthermore, the initial values of the input voltage and output voltage determine which MOSFET to operate in the saturation region.
From inspection of the circuit as shown in FIG. 2A, if the analog input voltage is larger than the data line voltage, then the n-MOSFET is in the saturation region and the p-MOSFET is cut off; however, if the analog input voltage is smaller than the data line voltage, then the p-MOSFET is in the saturation region and the n-MOSFET is cut off.
Please refer to FIG. 2B, which shows a waveform diagram for the switches SW1""s and SW2. The operation principle of the circuit shown in FIG. 2A can be explained with the waveform diagram shown in FIG. 2A. Please further refer to FIG. 3A and FIG. 3B, wherein the two SW1""s are ON and the SW2 is OFF for the circuit shown in FIG. 3A, and the two SW1""s are OFF and the SW2 is ON for the circuit shown in FIG. 3B. When the two SW1""s are ON, the SW2 is OFF, the analog input voltage is assumed to be in the range from 5 to 10 V, and the data line voltage is in the range from 0 to 5 V, then the analog input voltage is larger than the data line voltage, causing the n-MOSFET to be ON and the data line voltage to increase until Vgs=Vnth, the threshold voltage of the n-MOSFET. Meanwhile, the n-MOSFET is almost cut off, the storage voltage across the capacitor Cvt is Vnth, and the data line voltage is Vinxe2x88x92Vnth. After the capacitor Cvt has stored a voltage of Vnth, the two SW1""s are cut OFF and the SW2 turns ON, and the DAC voltage remains unchanged. Meanwhile, since the capacitor Cvt has stored a voltage of Vnth, the gate voltage of the n-MOSFET becomes Vin+Vnth, causing the n-MOSFET to operate in the saturation region and the data line voltage to increase until it reaches Vin.
Accordingly, it is obvious that, regardless of the Vth value, the final voltage on the data line approaches the output voltage Vin of the DAC, such that the problem that the threshold voltage varies can be overcome. However, such a circuit still has two major disadvantages to be improved, wherein (1) the circuit is modified by storing a voltage equal to the threshold voltage, however, the threshold voltage is not constant but varies with the current in the sub-threshold region, and it takes a long time for the threshold voltage to become stable; and (2) in operation, there is formed a xe2x80x9cdead zonexe2x80x9d, in which both of the two MOSFET""s are cut off when the variation of the input voltage Vin is smaller than |Vth|.
In addition, the operational feasibility of the circuit as shown in FIG. 3A has been examined by simulation. It has been found that, for different values of Vds, the corresponding Id-Vgs curves differ. As a result, Vout can not approach a final value. Furthermore, if the charging process lasts long enough, Vout may even exceed Vin and operate in the linear region. Such a circuit suffers from considerable inaccuracy and is not suitable for high-resolution applications. Consequently, there is a need for improved driving circuit.
In order to overcome the above problems, it is the primary object of the present invention to provide a source follower with Vgs compensation, such that the output voltage precisely follows the input voltage by various arrangements of MOSFET""s, switches, and capacitors. In addition, the output voltage of said source follower is equal to the input voltage of said source follower, without adding too many components to the circuit.
In order to accomplish the foregoing object, the present invention provides a source follower with Vgs compensation, comprising: a complementary MOS (to be abbreviated as CMOS below) circuit composed of a MOSFET M1 and a MOSFET M2, with the gate terminal of said MOSFET M1 connected to an input voltage Vin and the gate terminal of said MOSFET M2 connected to a capacitor C and a first switch SW1, wherein the other terminal of said first switch SW1 is connected to a constant current source and the source terminal of said MOSFET M1; and a capacitor C, with one terminal of said capacitor C connected between the gate terminal of said MOSFET M2 and said first switch SW1, and the other terminal connected between a second switch SW2 and the other first switch SW1, wherein the other terminal of said second switch SW2 is connected to an input voltage Vin and the other terminal of said the other first switch SW1 is connected to a constant current source, the source terminal of said MOSFET M2 and the load to provide a output voltage of Vout.
It is preferable that the circuit with the arrangement of said CMOS circuit, switches and capacitor can operate in Phase 1 mode (at time t1), wherein the voltage level starting from the input voltage Vin obtains a voltage rise of |Vgs| through said MOSFET M1 and then obtains a voltage drop of Vgs2 through said MOSFET M2, resulting in a gate voltage of said MOSFET M1 being equal to Vin+|Vgs1(t1)| and a voltage across the two terminals of said capacitor being equal to Vgs2(t1) of said MOSFET M2.
It is preferable that the circuit with the arrangement of said CMOS circuit, switches and capacitor can operate in Phase 2 mode (at time t2), wherein the input voltage is connected to one terminal of said capacitor, resulting in a gate voltage of said MOSFET M2 being equal to Vin+|Vgs2(t1)| and an output voltage Vout being equal to Vin+|Vgs2(t1)|xe2x88x92|Vgs2(t2)|, which is very close to Vin.
It is preferable that said CMOS circuit can be implemented by using a p-MOSFET as said MOSFET M1 and an n-MOSFET as said MOSFET M2.
It is preferable that said CMOS circuit can also be implemented by using an n-MOSFET as said MOSFET M1 and a p-MOSFET as said MOSFET M2.